Posts

system verilog assertion when $rose asserted two clock singnal are high

SVA important snippet module test;                   // property p;                   //initial                  //begin                         bit a;                           bit b;                          bit c;                         bit clk,rst;                     // always@(posedge clk)                      // a_cc: assert property(@(posedge clk)  $rose(a) |=> ##1 (b[=2]) ##2 c;                      // a_cc:assert property (p);  ...

perl important snippets

 perl important snippets:-    $a="ab"; $b="a"; if($a gt $b) { #print "true \n" } else print "false \n"; } ########snippets######### =pod      $var="Perl";      $var1='$var';      $var2= "$var";      print "$var1\n";      print "$var2\n"; =cut                  ############### arrays ################## =pod      @array=(1,2,"a","b");      print("@array\n"); =cut  ############# Hash ############### =pod                    %hash=("key"=>1,     "key2"=>2,             "key3"=>"a",     "key4"=>"b");             print(""); =cut ######## Arithmetic Opeartor ################ =pod     $x=5;     $y=10;     $z=$x+$y;     print("$z\n"); =cut ##...

perl important snippets

  perl important snippets:-    ########snippets######### =pod      $var="Perl";      $var1='$var';      $var2= "$var";      print "$var1\n";      print "$var2\n"; =cut          

perl important snippets

 perl important snippets:- $a="ab"; $b="a"; if($a gt $b) { #print "true \n" } else print "false \n"; }

system verilog examle thread code

 system verilog example thread code:- /*module threads(); initial begin fork for( int H1_pointer=0; H1_pointer<=2; H1_pointer++) begin #1  $display($time, " FIRST LOOP: vlaue of H1=%g", H1_pointer); end for(int D1_channel=2; D1_channel>=0; D1_channel--) begin #1 $display($time, " SECOND LOOP: vlaue of D1=%g", D1_channel); end join $display("@%g ouside of FORK-JOIN\n", $time); #3 $finish; end endmodule*/ /*module theads(); initial begin fork for( int H1_pointer=0; H1_pointer<=2; H1_pointer++) begin #1 $display($time, " FIRST LOOP: value of H1=%g", H1_pointer); end for( int D1_channel=2; D1_channel>=0; D1_channel--) begin #1 $display($time," SECOND LOOP: vlaue of D1=%g", D1_channel); end join_any $display("@%g outside of frok-join-any\n", $time); #3 $finish; end endmodule*/ /*module threads(); initial begin fork for( int h1_pointer=0; h1_pointer<=2; h1_pointer++) begin #1 $display($time," first loop: value of...

system verilog example fork join / fork join_none/ fork join_any example codes

*module test;  int d,result;   int a=2,b=3;       function automatic mult(input int a,input int b,output int c);        c=(a*b)+2;        $display("inside function");        $display("$time =%d,a=%d,b=%d,c=%d",$time,a,b,c);    endfunction      initial      fork        begin        #1;        mult(2,3,d);        $display("//////");        $display("$time =%d,a=%d,b=%d,d=%d",$time,a,b,d);       end       begin        #2;        mult(2,4,d);        $display("//////");        $display("$time =%d,a=%d,b=%d,d=%d",$time,a,b,d);       end    join endmodule*/ /*module test;  int d,result;   int a=2,b=3;      ...

system verilog queue using methods example code

 system verilog queue using methods example code:- first we know methods: push pop push front push back pop front pop back insert delete code:- /*module test; int k, q[$] ='{1,2,3,4,5,6}; initial begin foreach(q[i]) begin k=q.pop_back(); $display("%d",k); end $display("%p",q); end endmodule :test*/