uvm example snippet by using macros and without macros

uvm example snippets by using macros and without macros:-

/*import uvm_pkg::*;

`include "uvm_macros.svh"

class my_xtn extends uvm_sequence_item;

rand bit [3:0]addr;

rand bit [7:0] data;

string str;

constraint  valid_addr{addr inside {[2:13]};}

constraint  valid_data {data inside {[15:150]};}

`uvm_object_utils_begin(my_xtn)

`uvm_field_int(addr,UVM_ALL_ON)

`uvm_field_int(data,UVM_ALL_ON)

`uvm_object_utils_end

function new(string name="my_xtn");

super.new(name);

endfunction

endclass

module xtn_test();

my_xtn xtn,xtn1,xtn2,xtn3;

bit a[];

int unsigned b[];

initial

begin

function new("string name=

xtn=my_xtn::type_id::create();

assert(xtn.randomize());

xtn.print();

$display("%s", xtn.sprint());

xtn.str=$sformatf("%s",xtn.sprint());

$display("str=%s", xtn.str);

$cast(xtn1,xtn.clone());

xtn1.print();

$display(xtn.compare(xtn1));

xtn2=my_xtn::type_id::create("xtn2");

xtn2.copy(xtn1);

xtn2.print();

xtn2.pack(a);

$display(a);

xtn2.pack_ints(b);

$display(b);

xtn3=my_xtn::type_id::create("xtn3");

xtn3.unpack(a);

xtn3.print();

end

endmodule*/

/*import uvm_pkg::*;

`include "uvm_macros.svh"

class trans extends uvm_sequence_item;

`uvm_object_utils(trans)

rand bit [3:0] addr;

rand bit [7:0] data;

constraint c1{addr inside {[5:12]};

              data inside {[50:200]};}

function new(string name="trans");

super.new(name);

endfunction

function void do_copy(uvm_object rhs);

trans xtn;

if(!$cast(xtn,rhs))

`uvm_fatal("casting", "casting of an object is failed")

super.do_copy(rhs);

this.addr=xtn.addr;

this.data=xtn.data;

endfunction

function void do_print(uvm_printer printer);

super.do_print(printer);

printer.print_field("addr",addr,$size(addr),UVM_DEC);

printer.print_field("data",data,$size(data),UVM_DEC);

endfunction

function bit do_compare(uvm_object rhs,uvm_comparer comparer);

trans xtn;

if(!$cast(xtn,rhs))

begin

`uvm_fatal("casting", "casting of an object is failed")

return 'b0;

end

return

 super.do_compare(rhs,comparer) && 

this.addr==xtn.addr &&

 this.data==xtn.data;

endfunction

endclass

class my_test extends uvm_test;

`uvm_component_utils(my_test)

trans xtn,xtn1;

function new(string name="my_test", uvm_component parent=null);

super.new(name,parent);

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

xtn=trans::type_id::create("xtn");

xtn1=trans::type_id::create("xtn1");

`uvm_info("build_phase", "object_created",UVM_HIGH)

endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);

repeat(6)

begin

assert(xtn.randomize());

xtn.print();

`uvm_error(get_type_name(),"quit due to 10 error count");

end

xtn1.copy(xtn);

xtn1.print();

$display(xtn1.compare(xtn));

endtask

endclass

module top();

trans xtn;

initial

begin

run_test("my_test");

end

endmodule*/

/*import uvm_pkg::*;

`include "uvm_macros.svh"

class xtn extends uvm_sequence_item;

`uvm_object_utils(xtn)

typedef uvm_object_registry #(xtn,"SANJAY")

//type_id;

static function type_id::get_type();

return type_id::get();

endfunction

//used to get the type_name as a string

function string get_type_name();

return"SANJAY";

endfunction

rand bit [3:0]a;

constraint c1 {a==10;}

 

function new(string name="xtn");

super.new(name);

endfunction

virtual function void display();

$display("a=%0d", a);

$display("i am in base class");

endfunction

endclass

class small_xtn1 extends xtn;

`uvm_object_utils(xtn)

constraint c1 {a==15;}

function new(string name="small_xtn1");

super.new(name);

endfunction

function void display();

$display("i am in derived class");

endfunction

endclass

module top();

xtn x1;

initial

begin

x1=xtn::type_id::create("x1");

x1=new();

$display("%0d", x1);

$display(x1.get_type());

$display(x1.get_type.name());

x1.randomize();

x1.display();

factory.set_type_override_by_type(xtn::get_type(),

small_xtn1::get_type());

factory.print();

x1=new();

$display("%0d", x1);

$display(x1.get_type());

$display(x1 .get_type_name());

x1.randomize();

x1.display();

end

endmodule*/

import uvm_pkg::*;

`include "uvm_macros.svh"

class xtn extends uvm_sequence_item;

`uvm_object_utils(xtn)

function new(string name="xtn");

super.new(name);

endfunction

rand bit [3:0]addr;

rand bit [7;0]data;

`uvm_object_utils_begin(xtn)

`uvm_field_int(addr,UVM_ALL_ON)

`uvm_field_int(data,UVM_ALL_ON)

`uvm_object_utils_end

endclass

class my_seq extends uvm_component;

uvm_blocking_put_port #(xtn) put_port;

`uvm_component_utils(my_seq)

function new(string name="my_seq", uvm_component parent=null);

super.new(name,parent);

put_port=new("pull_port", this);

endfunction

virtual task run_phase(uvm_phase phase);

xtn xtn1;

super.run_phase(phase);

repeat(2)

begin

xtn1=xtn::type_id::create("xtn1");

assert(xtn1.randomize());

xtn1.print();

`uvm_info(get_type_name(),"packet generated",UVM_LOW);

phase.raise_objection(this);

#10 put_port.put(xtn1);

phase.drop_objection(this);

end

endtask

virtual function void extract_phase(uvm_phase phase);

super.extract_phase(phase);

`uvm_info(get_type_name(),"test extract phase", UVM_LOW)

endfunction

endclass

class my_test extends uvm_test;

`uvm_component_utils(my_test)

my_seq seq;

my_drv drvh;

function new(string name="my_test", uvm_component parent=null);

super.new(name,parent);

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase0;

seq=my_seq::type_id::create("seq", this);

drvh=my_seq::type_id::create("drvh", this);

endfunction

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

seq.put_port.connect(drvh.put_imp1);

endfunction

function void end_of_elobration_phase(uvm_phase phase);

super.end_of_elobration_phase(phase);

`uvm_top.print_topology();

endfunction

endclass

module top();

initial

begin

run_test("my_test");

initial

begin

#1000;

`uvm_top.stop_request();

end

endmodule