verilog basic RTL coding day-1

first of all we all know the any RTL code in Verilog. we can write in three methods.

1. data flow modelling

2.  gate level modelling

3. behaviour level modelling

every code we write by using truth table and schematic diagram

 full adder:- data flow modelling

module full_adder(a, b, c, sum, carry);

input a, b, c;

output reg sum, carry;

initial

begin

assign  sum = (a^b^c);

assign carry = (a&b)|(b&c)|(c&a);

end

endmodule

full adder:- behaviour level modelling

module full_adder(a,b,c,sum,carry);

input a.b.c;

output reg sum, carry;

always@(a or b or c)

begin

sum = a^b^c;

carry=(a&b)|(b&c)|(c&a);

end

endmodule

full adder:- gate level modelling

module full_adder(a,b,c,sum,carry);

input a,b,c;

output reg sum,carry;

wire x1,x2,x3;

xor(x1,a,b);

and(x3,a,b);

xor(sum,x1,c);

and(x2,x1,c);

or(carry,x2,x3);

endmodule