verilog important codes
verilog important codes:-
Lab1:Verilog
Abstraction Levels:-
1. Write a verilog
code for a half adder adder using data
flow abstraction using testbench
2. Write a verilog for a 1 bit full adder using 2 half adder and 1 or gate and verify using testbench
3. Write a verilog code for a full adder adder using data flow abstraction and verify using testbench
4. Write an RTL and testbench for 2:4 decoder using data flow abstraction
5. Write an RTL and testbench for a 4:1 MUX using 2:1 MUX
6. Write an RTL for a bidirectional buffer and verify the same using testbench.
7. Write an RTL and testbench and testbench for a 4 bit Ripple carry adder using 1 bit full adder
8. Write an RTL for 4X1 mux using decoder and tri state buffer and verify the same using testbench
9. write 8:3 priority encoder using a structural modelLab2:Verilog
Operators:-
1. Work on Operators.
2. Write an RTL and Testbench for ALU using arithmetic
operators.
Lab3:Combinational
Logic:-
1.Write behavioral description and test bench for 4:1 MUX.
2.Write a behavioral description for a 3:8 decoder and verify using a test bench.
3.Write a behavioral description and testbench 8:3 priority encoder.
Write a verilog code for a half adder adder using data flow abstraction using testbench
RTL CODE:
// Half Adder using Data Flow Abstraction
module half_adder (
input wire a, // First input
input wire b, // Second input
output wire sum, // Sum output
output wire carry // Carry output
);
// Data flow assignments
assign sum = a ^ b; // Sum is the XOR of a and b
assign carry = a & b; // Carry is the AND of a and b
endmodule.
TESTBENCH:
module tb_half_adder;
// Testbench signals
reg a;
reg b;
wire sum;
wire carry;
// Instantiate the half adder
half_adder uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
// Test sequence
initial begin
// Initialize inputs
a = 0; b = 0;
// Apply test vectors
#10 a = 0; b = 1; // Test case 1: a=0, b=1
#10 a = 1; b = 0; // Test case 2: a=1, b=0
#10 a = 1; b = 1; // Test case 3: a=1, b=1
// End of simulation
#10;
$finish;
end
// Monitor output
initial begin
$monitor("Time: %0t | A: %b | B: %b | Sum: %b | Carry: %b", $time, a, b, sum, carry);
end
endmodule.
SYNTHESIS:
SIMULATION:-
2. Write a verilog for a 1 bit full adder using 2 half adder and 1 or gate and verify using testbench
RTL CODE:
module half_adder(input a, b, output sum, carry);
assign sum = a ^ b;
assign carry = a & b;
endmodule
module full_adder(input a, b, cin, output sum, cout);
wire sum1, carry1, carry2;
// First half adder
half_adder HA1 (.a(a), .b(b), .sum(sum1), .carry(carry1));
// Second half adder
half_adder HA2 (.a(sum1), .b(cin), .sum(sum), .carry(carry2));
// OR gate for the final carry out
assign cout = carry1 | carry2;
endmodule.
TESTBENCH:
// Testbench for the full adder
module testbench;
reg a, b, cin;
wire sum, cout;
// Instantiate the full adder
full_adder FA1 (.a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));
// Apply input values
initial begin
a = 1;
b = 1;
cin = 0;
// Display input values
$display("Inputs: a = %b, b = %b, cin = %b", a, b, cin);
// Display output values
$display("Sum = %b, Cout = %b", sum, cout);
// Change input values and display results
#5 a = 0; b = 1; cin = 1;
$display("Inputs: a = %b, b = %b, cin = %b", a, b, cin);
$display("Sum = %b, Cout = %b", sum, cout);
// Add more test cases as needed
// ...
// Stop simulation
#10 $finish;
end
endmodule.
SYNTHESIS:
SIMULATION:-
3. Write a verilog code for a full adder adder using data flow abstraction and verify using testbench
RTL CODE:
// Half Adder Module
module half_adder (
input a, // First input bit
input b, // Second input bit
output sum, // Sum output
output carry // Carry output
);
assign sum = a ^ b; // Sum is the XOR of a and b
assign carry = a & b; // Carry is the AND of a and b
endmodule
// Full Adder Module
module full_adder (
input a, // First input bit
input b, // Second input bit
input cin, // Carry-in
output sum, // Sum output
output carry // Carry output
);
// Internal wires for half adder outputs
wire sum1, carry1, carry2;
// Instantiate two half adders
half_adder HA1 (
.a(a),
.b(b),
.sum(sum1),
.carry(carry1)
);
half_adder HA2 (
.a(sum1),
.b(cin),
.sum(sum),
.carry(carry2)
);
// OR gate to combine carry outputs
assign carry = carry1 | carry2;
endmodule
TESTBENCH:
module tb_full_adder;
// Inputs
reg a;
reg b;
reg cin;
// Outputs
wire sum;
wire carry;
// Instantiate the full adder
full_adder uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.carry(carry)
);
// Initialize inputs and apply test cases
initial begin
// Initialize inputs
a = 0;
b = 0;
cin = 0;
// Wait for global reset to finish
#10;
// Apply test vectors
a = 0; b = 0; cin = 0; #10; // Expected: sum = 0, carry = 0
a = 0; b = 0; cin = 1; #10; // Expected: sum = 1, carry = 0
a = 0; b = 1; cin = 0; #10; // Expected: sum = 1, carry = 0
a = 0; b = 1; cin = 1; #10; // Expected: sum = 0, carry = 1
a = 1; b = 0; cin = 0; #10; // Expected: sum = 1, carry = 0
a = 1; b = 0; cin = 1; #10; // Expected: sum = 0, carry = 1
a = 1; b = 1; cin = 0; #10; // Expected: sum = 0, carry = 1
a = 1; b = 1; cin = 1; #10; // Expected: sum = 1, carry = 1
// End simulation
$finish;
end
// Monitor changes
initial begin
$monitor("Time = %0d, a = %b, b = %b, cin = %b, sum = %b, carry = %b", $time, a, b, cin, sum, carry);
End.
SYNTHESIS:
SIMULATION
4. Write an RTL and testbench for 2:4 decoder using data flow abstraction
RTL CODE:
module Decoder_2to4 (
input [1:0] in,
output [3:0] out
);
assign out[0] = (in == 2'b00) ? 1'b1 : 1'b0;
assign out[1] = (in == 2'b01) ? 1'b1 : 1'b0;
assign out[2] = (in == 2'b10) ? 1'b1 : 1'b0;
assign out[3] = (in == 2'b11) ? 1'b1 : 1'b0;
endmodule.
TESTBENCH:
module tb_Decoder_2to4;
reg [1:0] in;
wire [3:0] out;
Decoder_2to4 uut (
.in(in),
.out(out)
);
initial begin
// Test case 1: in = 2'b00
in = 2'b00;
#10 $display("Input: %b, Output: %b", in, out);
// Test case 2: in = 2'b01
in = 2'b01;
#10 $display("Input: %b, Output: %b", in, out);
// Test case 3: in = 2'b10
in = 2'b10;
#10 $display("Input: %b, Output: %b", in, out);
// Test case 4: in = 2'b11
in = 2'b11;
#10 $display("Input: %b, Output: %b", in, out);
// Add more test cases as needed
// Terminate simulation
#10 $finish;
end
endmodule.
SYNTHESIS:
SIMULATION:
5. Write an RTL and testbench for a 4:1 MUX using 2X1 mux
RTL CODE:-
// 2-to-1 MUX
module mux_2to1 (
input wire a, // Input A
input wire b, // Input B
input wire sel, // Select signal
output wire out // Output
);
assign out = (sel) ? b : a; // Select between a and b based on sel
endmodule
// 4-to-1 MUX using 2-to-1 MUXes
module mux_4to1 (
input wire [3:0] data, // 4-bit input data
input wire [1:0] sel, // 2-bit select signal
output wire out // Output
);
wire mux0_out, mux1_out; // Intermediate outputs of 2-to-1 MUXes
// Instantiate two 2-to-1 MUXes
mux_2to1 mux0 (
.a(data[0]),
.b(data[1]),
.sel(sel[0]),
.out(mux0_out)
);
mux_2to1 mux1 (
.a(data[2]),
.b(data[3]),
.sel(sel[0]),
.out(mux1_out)
);
// Final 2-to-1 MUX to select between the two intermediate outputs
mux_2to1 mux2 (
.a(mux0_out),
.b(mux1_out),
.sel(sel[1]),
.out(out)
);
endmodule
TESTBENCH:
module tb_mux_4to1;
// Testbench signals
reg [3:0] data;
reg [1:0] sel;
wire out;
// Instantiate the 4-to-1 MUX
mux_4to1 uut (
.data(data),
.sel(sel),
.out(out)
);
// Test sequence
initial begin
// Initialize inputs
data = 4'b0000;
sel = 2'b00;
// Apply test vectors
#10 data = 4'b1010; sel = 2'b00; // Output should be 1 (data[0])
#10 data = 4'b1010; sel = 2'b01; // Output should be 0 (data[1])
#10 data = 4'b1010; sel = 2'b10; // Output should be 1 (data[2])
#10 data = 4'b1010; sel = 2'b11; // Output should be 0 (data[3])
// End of simulation
#10;
$finish;
end
// Monitor output
initial begin
$monitor("Time: %0t | Data: %b | Sel: %b | Out: %b", $time, data, sel, out);
end
endmodule
SYNTHESIS:
SIMULATION:
6. Write an RTL for a bidirectional buffer and verify the same using testbench.
RTL CODE:
// Bidirectional Buffer
module bidirectional_buffer (
input wire clk,
input wire enable,
input wire dir, // Direction control: 0 for input, 1 for output
inout wire data // Bidirectional data line
);
// Internal signal for data
reg data_reg;
// Buffer control logic
always @(posedge clk) begin
if (enable) begin
if (dir) begin
// Output mode: Drive data onto the bus
data_reg <= data_reg;
end
else begin
// Input mode: Read data from the bus
data_reg <= data;
end
end
end
// Tri-state buffer logic
assign data = (enable && !dir) ? data_reg : 1'bz; // High impedance when not in input mode
endmodule.
TESTBENCH:
module tb_bidirectional_buffer;
// Testbench signals
reg clk;
reg enable;
reg dir;
reg [7:0] data_in;
wire [7:0] data_out;
// Instantiate the bidirectional buffer
bidirectional_buffer uut (
.clk(clk),
.enable(enable),
.dir(dir),
.data(data_out)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // 10 ns clock period
end
// Test sequence
initial begin
// Initialize signals
enable = 0;
dir = 0;
data_in = 8'h00;
// Test case 1: Write data
#10;
enable = 1;
dir = 1; // Set direction to output
data_in = 8'hA5;
// Wait for some time
#10;
enable = 0;
// Test case 2: Read data
#10;
dir = 0; // Set direction to input
enable = 1;
// Wait and observe the data
#10;
enable = 0;
// End of simulation
#10;
$finish;
end
// Monitor output
initial begin
$monitor("Time: %0t | Enable: %b | Dir: %b | Data In: %h | Data Out: %h", $time, enable, dir, data_in, data_out);
end
endmodule
SYNTHESIS:
SIMULATION:-
7. Write an RTL and testbench and testbench for a 4 bit Ripple carry adder using 1 bit full adder
RTL CODE:
`timescale 1ns / 1ps
// 1-bit Full Adder
module full_adder (
input wire a, // First input
input wire b, // Second input
input wire cin, // Carry input
output wire sum, // Sum output
output wire cout // Carry output
);
assign {cout, sum} = a + b + cin;
endmodule
// 4-bit Ripple Carry Adder
module ripple_carry_adder (
input wire [3:0] a, // 4-bit input A
input wire [3:0] b, // 4-bit input B
input wire cin, // Carry input
output wire [3:0] sum, // 4-bit sum output
output wire cout // Carry output
);
// Internal carry signals
wire c1, c2, c3;
// Instantiate 1-bit full adders
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c1)
);
full_adder fa1 (
.a(a[1]),
.b(b[1]),
.cin(c1),
.sum(sum[1]),
.cout(c2)
);
full_adder fa2 (
.a(a[2]),
.b(b[2]),
.cin(c2),
.sum(sum[2]),
.cout(c3)
);
full_adder fa3 (
.a(a[3]),
.b(b[3]),
.cin(c3),
.sum(sum[3]),
.cout(cout)
);
Endmodule.
TESTBENCH:-
module tb_ripple_carry_adder;
// Testbench signals
reg [3:0] a;
reg [3:0] b;
reg cin;
wire [3:0] sum;
wire cout;
// Instantiate the 4-bit ripple carry adder
ripple_carry_adder uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
// Test sequence
initial begin
// Initialize inputs
a = 4'b0000;
b = 4'b0000;
cin = 0;
// Apply test vectors
#10 a = 4'b0001; b = 4'b0010; cin = 0;
#10 a = 4'b0101; b = 4'b0101; cin = 0;
#10 a = 4'b1111; b = 4'b0001; cin = 1;
#10 a = 4'b1010; b = 4'b0101; cin = 1;
#10 a = 4'b1111; b = 4'b1111; cin = 0;
// End of simulation
#10;
$finish;
end
// Monitor output
initial begin
$monitor("Time: %0t | A: %b | B: %b | Cin: %b | Sum: %b | Cout: %b", $time, a, b, cin, sum, cout);
end
endmodule
SYNTHESIS:
SIMULATION:
8. Write an RTL for 4X1 mux using decoder and tri state buffer and verify the same using testbench
RTL CODE:-
// 2-to-4 Decoder
module decoder_2to4 (
input wire [1:0] sel, // 2-bit select input
output wire [3:0] dout // 4-bit output
);
assign dout = (sel == 2'b00) ? 4'b0001 :
(sel == 2'b01) ? 4'b0010 :
(sel == 2'b10) ? 4'b0100 :
4'b1000;
endmodule
// 4x1 MUX
module mux_4x1 (
input wire [3:0] data_in, // 4-bit data inputs
input wire [1:0] sel, // 2-bit select input
output wire dout // Output
);
wire [3:0] sel_out; // Outputs from the decoder
// Instantiate the 2-to-4 decoder
decoder_2to4 dec (
.sel(sel),
.dout(sel_out)
);
// Tri-state buffer for each input
assign dout = (sel_out[0]) ? data_in[0] :
(sel_out[1]) ? data_in[1] :
(sel_out[2]) ? data_in[2] :
(sel_out[3]) ? data_in[3] : 1'bz;
endmodule
TESTBENCH:
: module tb_mux_4x1;
// Testbench signals
reg [3:0] data_in;
reg [1:0] sel;
wire dout;
// Instantiate the 4x1 MUX
mux_4x1 uut (
.data_in(data_in),
.sel(sel),
.dout(dout)
);
// Test sequence
initial begin
// Initialize inputs
data_in = 4'b0000;
sel = 2'b00;
// Apply test vectors
#10 data_in = 4'b1010; sel = 2'b00; // Output should be 1
#10 data_in = 4'b1010; sel = 2'b01; // Output should be 0
#10 data_in = 4'b1010; sel = 2'b10; // Output should be 1
#10 data_in = 4'b1010; sel = 2'b11; // Output should be 0
// End of simulation
#10;
$finish;
end
// Monitor output
initial begin
$monitor("Time: %0t | Data In: %b | Sel: %b | Dout: %b", $time, data_in, sel, dout);
end
endmodule
SYNTHESIS:
SIMULATION:-
9. write 8:3 priority encoder using a structural model.
RTL CODE:-
`
module priority_encoder_8to3 (
input wire [7:0] in, // 8-bit input
output wire [2:0] out, // 3-bit encoded output
output wire valid // Indicates if any input is active
);
// Internal wires for priority levels
wire [7:0] level;
// Priority logic: Set 'level' based on highest active input
assign level[7] = in[7];
assign level[6] = in[7] | in[6];
assign level[5] = in[7] | in[6] | in[5];
assign level[4] = in[7] | in[6] | in[5] | in[4];
assign level[3] = in[7] | in[6] | in[5] | in[4] | in[3];
assign level[2] = in[7] | in[6] | in[5] | in[4] | in[3] | in[2];
assign level[1] = in[7] | in[6] | in[5] | in[4] | in[3] | in[2] | in[1];
assign level[0] = in[7] | in[6] | in[5] | in[4] | in[3] | in[2] | in[1] | in[0];
// Output assignment: Encode priority
assign out[2] = level[7] | level[6] | level[5] | level[4];
assign out[1] = level[7] | level[6] | level[5] | level[3] | level[2];
assign out[0] = level[7] | level[6] | level[4] | level[3] | level[1] | level[0];
// Valid output indicates if any input is active
assign valid = |in;
endmodule
TESTBENCH:-
module tb_priority_encoder8to3;
// Inputs
reg [7:0] in;
// Outputs
wire [2:0] out;
wire valid;
// Instantiate the priority encoder
priority_encoder8to3 uut (
.in(in),
.out(out),
.valid(valid)
);
// Initialize inputs and apply test cases
initial begin
// Apply test cases
in = 8'b00000000; #10; // Expected: out = 3'b000, valid = 0
in = 8'b00000001; #10; // Expected: out = 3'b000, valid = 1
in = 8'b00000010; #10; // Expected: out = 3'b001, valid = 1
in = 8'b00000100; #10; // Expected: out = 3'b010, valid = 1
in = 8'b00001000; #10; // Expected: out = 3'b011, valid = 1
in = 8'b00010000; #10; // Expected: out = 3'b100, valid = 1
in = 8'b00100000; #10; // Expected: out = 3'b101, valid = 1
in = 8'b01000000; #10; // Expected: out = 3'b110, valid = 1
in = 8'b10000000; #10; // Expected: out = 3'b111, valid = 1
// Test case where multiple inputs are active
in = 8'b11100000; #10; // Expected: out = 3'b111, valid = 1
// End simulation
$finish;
end
// Monitor changes
initial begin
$monitor("Time = %0d, in = %b, out = %b, valid = %b", $time, in, out, valid);
end
endmodule
Synthesis:-
Simulation:-
Lab2:Verilog
Operators:-
1. Work on Operators
RTL CODE:-
module operators (
input [3:0] a, b, // Assuming 4-bit inputs
output reg y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, y12, y13, y14, y15, y16, y17, y18, y19, y20, y21, y22, y23, y24, y25, y26, y27, y28, y29, y30
);
always @(*) begin
y0 = a && b; // Logical AND
y1 = ~b; // NOT (fixed from 'allb' to '~b')
y2 = !a; // Logical NOT
y3 = a & b; // Bitwise AND
y4 = a | b; // Bitwise OR (fixed from 'alb' to 'a | b')
y5 = ~a; // Bitwise NOT
y6 = a ^ b; // Bitwise XOR
y7 = a ~^ b; // Bitwise XNOR
y8 = &a; // Reduction AND
y9 = !a; // Logical NOT
y10 = ~&a; // Reduction NAND
y11 = ~a; // Bitwise NOT (redundant, but correct)
y12 = ^a; // Reduction XOR
y13 = ~^a; // Reduction XNOR
y14 = a << b; // Logical left shift
y15 = a >> b; // Logical right shift
y16 = a >>> b; // Arithmetic right shift
y17 = a <<< b; // Arithmetic left shift
y18 = a > b; // Greater than
y19 = a >= b; // Greater than or equal to (fixed from '4>=b' to 'a >= b')
y20 = a < b; // Less than
y21 = a <= b; // Less than or equal to
y22 = (a == b); // Equality
y23 = a - b; // Subtraction (fixed from 'al-b' to 'a - b')
y24 = (a === b); // Case equality
y25 = (a !== b); // Case inequality
y26 = a + b; // Addition
y27 = a - b; // Subtraction
y28 = a * b; // Multiplication
y29 = a / b; // Division
y30 = a % b; // Modulus
end
endmodule
synthesis:
2. Write an RTL and Testbench for ALU using arithmetic
Operators
RTL CODE:-
`timescale 1ns / 1ps
module alu(
input [7:0] a, b,
input [3:0] command_in,
input oe,
output [15:0] d_out
);
reg [15:0] out; // Declare 'out' as a register to store intermediate results
// Define command codes using parameters
parameter ADD = 4'b0000,
SUB = 4'b0001,
INC = 4'b0010,
DEC = 4'b0011,
MUL = 4'b0100,
DIV = 4'b0101,
SHL = 4'b0110,
SHR = 4'b0111,
AND = 4'b1000,
OR = 4'b1001,
INV = 4'b1010,
NAND = 4'b1011,
NOR = 4'b1100,
XOR = 4'b1101,
XNOR = 4'b1110,
BUF = 4'b1111;
// Always block to determine the output based on the command
always @(command_in or a or b) begin
case (command_in)
ADD: out = a + b;
SUB: out = a - b;
INC: out = a + 1;
DEC: out = a - 1;
MUL: out = a * b;
DIV: out = a / b;
SHL: out = a << b;
SHR: out = a >> b;
AND: out = a & b;
OR: out = a | b;
INV: out = ~a;
NAND: out = ~(a & b);
NOR: out = ~(a | b);
XOR: out = a ^ b;
XNOR: out = ~(a ^ b);
BUF: out = a;
default: out = 16'h0000;
endcase
end
// Assign the output based on the oe signal
assign d_out = (oe) ? out : 16'hzzzz;
endmodule
TESTBENCH:-
`timescale 1ns / 1ps
module alu_tb();
reg [7:0] a, b;
reg [3:0] command;
reg enable;
wire [15:0] out;
integer m, n, o;
parameter
ADD = 4'b0000,
INC = 4'b0001,
SUB = 4'b0010,
DEC = 4'b0011,
MUL = 4'b0100,
DIV = 4'b0101,
SHL = 4'b0110,
SHR = 4'b0111,
AND = 4'b1000,
OR = 4'b1001,
INV = 4'b1010,
NAND = 4'b1011,
NOR = 4'b1100,
XOR = 4'b1101,
XNOR = 4'b1110,
BUF = 4'b1111;
task initialize;
begin
a = 8'b0;
b = 8'b0;
command = ADD;
enable = 1'b0;
end
endtask
task en_oe(input en);
begin
enable = en;
end
endtask
task inputs(input [7:0] j, k);
begin
a = j;
b = k;
end
endtask
task delay;
begin
#10;
end
endtask
always @(command)
begin
#10; // Command processing delay
case (command)
ADD : $display("Command: ADD");
INC : $display("Command: INC");
SUB : $display("Command: SUB");
DEC : $display("Command: DEC");
MUL : $display("Command: MUL");
DIV : $display("Command: DIV");
SHL : $display("Command: SHL");
SHR : $display("Command: SHR");
AND : $display("Command: AND");
OR : $display("Command: OR");
INV : $display("Command: INV");
NAND : $display("Command: NAND");
NOR : $display("Command: NOR");
XOR : $display("Command: XOR");
XNOR : $display("Command: XNOR");
BUF : $display("Command: BUF");
default: $display("Invalid command");
endcase
end
initial begin
initialize;
en_oe(1'b1);
for (m = 0; m < 16; m = m + 1) begin
command = m;
delay;
end
inputs(8'd20, 8'd10);
delay;
en_oe(1'b1);
inputs(8'd25, 8'd17);
command = ADD;
delay;
$finish;
end
initial
$monitor("Input enable=%b, a=%b, b=%b, command=%b, out=%b", enable, a, b, command, out);
Endmodule
Synthesis:-
Simulation:-
Lab3:Combinational
Logic:-
1.Write behavioral description and test bench for 4:1 MUX.
RTL CODE:-
module mux4to1 (
input [1:0] sel, // 2-bit select input
input [3:0] d, // 4-bit data input
output reg y // Output
);
always @(*) begin
case (sel)
2'b00: y = d[0]; // Select input 0
2'b01: y = d[1]; // Select input 1
2'b10: y = d[2]; // Select input 2
2'b11: y = d[3]; // Select input 3
default: y = 1'b0; // Default case
endcase
end
endmodule
TESTBENCH:-
`timescale 1ns / 1ps
module tb_mux4to1;
// Inputs
reg [1:0] sel;
reg [3:0] d;
// Output
wire y;
// Instantiate the multiplexer
mux4to1 uut (
.sel(sel),
.d(d),
.y(y)
);
// Initialize inputs and apply test cases
initial begin
// Initialize inputs
sel = 2'b00;
d = 4'b0000;
// Wait for global reset to finish
#10;
// Apply test vectors
d = 4'b1010; // Data input
sel = 2'b00; #10; // Expected output: y = d[0] = 1
sel = 2'b01; #10; // Expected output: y = d[1] = 0
sel = 2'b10; #10; // Expected output: y = d[2] = 1
sel = 2'b11; #10; // Expected output: y = d[3] = 0
// Change data input and repeat tests
d = 4'b1100; // New data input
sel = 2'b00; #10; // Expected output: y = d[0] = 0
sel = 2'b01; #10; // Expected output: y = d[1] = 0
sel = 2'b10; #10; // Expected output: y = d[2] = 1
sel = 2'b11; #10; // Expected output: y = d[3] = 1
// End simulation
$finish;
end
// Monitor changes
initial begin
$monitor("Time = %0d, sel = %b, d = %b, y = %b", $time, sel, d, y);
end
endmodule
Synthesis:-
Simulation:-
2.Write a behavioral description for a 3:8 decoder and verify using a test bench.
RTL CODE:-
module decoder3to8 (
input [2:0] in, // 3-bit input
input en, // Enable signal
output reg [7:0] out // 8-bit output
);
always @(*) begin
if (en) begin
case (in)
3'b000: out = 8'b00000001;
3'b001: out = 8'b00000010;
3'b010: out = 8'b00000100;
3'b011: out = 8'b00001000;
3'b100: out = 8'b00010000;
3'b101: out = 8'b00100000;
3'b110: out = 8'b01000000;
3'b111: out = 8'b10000000;
default: out = 8'b00000000; // Default case
endcase
end else begin
out = 8'b00000000; // Outputs are all zero when enable is low
end
end
TESTBENCH:-
module tb_decoder3to8;
// Inputs
reg [2:0] in;
reg en;
// Outputs
wire [7:0] out;
// Instantiate the decoder
decoder3to8 uut (
.in(in),
.en(en),
.out(out)
);
// Initialize inputs and apply test cases
initial begin
// Initialize inputs
in = 3'b000;
en = 0;
// Wait for global reset to finish
#10;
// Enable decoder and test all input combinations
en = 1;
// Apply test vectors
in = 3'b000; #10; // Check if out = 8'b00000001
in = 3'b001; #10; // Check if out = 8'b00000010
in = 3'b010; #10; // Check if out = 8'b00000100
in = 3'b011; #10; // Check if out = 8'b00001000
in = 3'b100; #10; // Check if out = 8'b00010000
in = 3'b101; #10; // Check if out = 8'b00100000
in = 3'b110; #10; // Check if out = 8'b01000000
in = 3'b111; #10; // Check if out = 8'b10000000
// Disable decoder and check output
en = 0;
in = 3'b000; #10; // Check if out = 8'b00000000
// End simulation
$finish;
end
// Monitor changes
initial begin
$monitor("Time = %0d, in = %b, en = %b, out = %b", $time, in, en, out);
end
endmodule
endmodule
synthesis:-
simulation:-
3.Write a behavioral description and testbench 8:3 priority encoder.
RTL CODE:-
module priority_encoder8to3 (
input wire [7:0] in, // 8-bit input
output reg [2:0] out, // 3-bit output (encoded value)
output reg valid // Indicates if at least one input is active
);
always @(*) begin
// Default values
out = 3'b000;
valid = 1'b0;
// Check for the highest-priority active input
if (in[7]) begin
out = 3'b111; // Highest priority input is 7
valid = 1'b1;
end
else if (in[6]) begin
out = 3'b110; // Highest priority input is 6
valid = 1'b1;
end
else if (in[5]) begin
out = 3'b101; // Highest priority input is 5
valid = 1'b1;
end
else if (in[4]) begin
out = 3'b100; // Highest priority input is 4
valid = 1'b1;
end
else if (in[3]) begin
out = 3'b011; // Highest priority input is 3
valid = 1'b1;
end
else if (in[2]) begin
out = 3'b010; // Highest priority input is 2
valid = 1'b1;
end
else if (in[1]) begin
out = 3'b001; // Highest priority input is 1
valid = 1'b1;
end
else if (in[0]) begin
out = 3'b000; // Highest priority input is 0
valid = 1'b1;
end
else begin
valid = 1'b0; // No inputs are active
end
end
endmodule
testbench:-
module tb_priority_encoder8to3;
// Inputs
reg [7:0] in;
// Outputs
wire [2:0] out;
wire valid;
// Instantiate the priority encoder
priority_encoder8to3 uut (
.in(in),
.out(out),
.valid(valid)
);
// Initialize inputs and apply test cases
initial begin
// Apply test cases
in = 8'b00000000; #10; // Expected: out = 3'b000, valid = 0
in = 8'b00000001; #10; // Expected: out = 3'b000, valid = 1
in = 8'b00000010; #10; // Expected: out = 3'b001, valid = 1
in = 8'b00000100; #10; // Expected: out = 3'b010, valid = 1
in = 8'b00001000; #10; // Expected: out = 3'b011, valid = 1
in = 8'b00010000; #10; // Expected: out = 3'b100, valid = 1
in = 8'b00100000; #10; // Expected: out = 3'b101, valid = 1
in = 8'b01000000; #10; // Expected: out = 3'b110, valid = 1
in = 8'b10000000; #10; // Expected: out = 3'b111, valid = 1
// Test case where multiple inputs are active
in = 8'b11100000; #10; // Expected: out = 3'b111, valid = 1
// End simulation
$finish;
end
// Monitor changes
initial begin
$monitor("Time = %0d, in = %b, out = %b, valid = %b", $time, in, out, valid);
end
endmodule
synthesis:-
simulation:-
RTL CODE:
// Half Adder using Data Flow Abstraction
module half_adder (
input wire a, // First input
input wire b, // Second input
output wire sum, // Sum output
output wire carry // Carry output
);
// Data flow assignments
assign sum = a ^ b; // Sum is the XOR of a and b
assign carry = a & b; // Carry is the AND of a and b
endmodule.
TESTBENCH:
module tb_half_adder;
// Testbench signals
reg a;
reg b;
wire sum;
wire carry;
// Instantiate the half adder
half_adder uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
// Test sequence
initial begin
// Initialize inputs
a = 0; b = 0;
// Apply test vectors
#10 a = 0; b = 1; // Test case 1: a=0, b=1
#10 a = 1; b = 0; // Test case 2: a=1, b=0
#10 a = 1; b = 1; // Test case 3: a=1, b=1
// End of simulation
#10;
$finish;
end
// Monitor output
initial begin
$monitor("Time: %0t | A: %b | B: %b | Sum: %b | Carry: %b", $time, a, b, sum, carry);
end
endmodule.
SYNTHESIS:
SIMULATION:-
2. Write a verilog for a 1 bit full adder using 2 half adder and 1 or gate and verify using testbench
RTL CODE:
module half_adder(input a, b, output sum, carry);
assign sum = a ^ b;
assign carry = a & b;
endmodule
module full_adder(input a, b, cin, output sum, cout);
wire sum1, carry1, carry2;
// First half adder
half_adder HA1 (.a(a), .b(b), .sum(sum1), .carry(carry1));
// Second half adder
half_adder HA2 (.a(sum1), .b(cin), .sum(sum), .carry(carry2));
// OR gate for the final carry out
assign cout = carry1 | carry2;
endmodule.
TESTBENCH:
// Testbench for the full adder
module testbench;
reg a, b, cin;
wire sum, cout;
// Instantiate the full adder
full_adder FA1 (.a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));
// Apply input values
initial begin
a = 1;
b = 1;
cin = 0;
// Display input values
$display("Inputs: a = %b, b = %b, cin = %b", a, b, cin);
// Display output values
$display("Sum = %b, Cout = %b", sum, cout);
// Change input values and display results
#5 a = 0; b = 1; cin = 1;
$display("Inputs: a = %b, b = %b, cin = %b", a, b, cin);
$display("Sum = %b, Cout = %b", sum, cout);
// Add more test cases as needed
// ...
// Stop simulation
#10 $finish;
end
endmodule.
SYNTHESIS:
SIMULATION:-
3. Write a verilog code for a full adder adder using data flow abstraction and verify using testbench
RTL CODE:
// Half Adder Module
module half_adder (
input a, // First input bit
input b, // Second input bit
output sum, // Sum output
output carry // Carry output
);
assign sum = a ^ b; // Sum is the XOR of a and b
assign carry = a & b; // Carry is the AND of a and b
endmodule
// Full Adder Module
module full_adder (
input a, // First input bit
input b, // Second input bit
input cin, // Carry-in
output sum, // Sum output
output carry // Carry output
);
// Internal wires for half adder outputs
wire sum1, carry1, carry2;
// Instantiate two half adders
half_adder HA1 (
.a(a),
.b(b),
.sum(sum1),
.carry(carry1)
);
half_adder HA2 (
.a(sum1),
.b(cin),
.sum(sum),
.carry(carry2)
);
// OR gate to combine carry outputs
assign carry = carry1 | carry2;
endmodule
TESTBENCH:
module tb_full_adder;
// Inputs
reg a;
reg b;
reg cin;
// Outputs
wire sum;
wire carry;
// Instantiate the full adder
full_adder uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.carry(carry)
);
// Initialize inputs and apply test cases
initial begin
// Initialize inputs
a = 0;
b = 0;
cin = 0;
// Wait for global reset to finish
#10;
// Apply test vectors
a = 0; b = 0; cin = 0; #10; // Expected: sum = 0, carry = 0
a = 0; b = 0; cin = 1; #10; // Expected: sum = 1, carry = 0
a = 0; b = 1; cin = 0; #10; // Expected: sum = 1, carry = 0
a = 0; b = 1; cin = 1; #10; // Expected: sum = 0, carry = 1
a = 1; b = 0; cin = 0; #10; // Expected: sum = 1, carry = 0
a = 1; b = 0; cin = 1; #10; // Expected: sum = 0, carry = 1
a = 1; b = 1; cin = 0; #10; // Expected: sum = 0, carry = 1
a = 1; b = 1; cin = 1; #10; // Expected: sum = 1, carry = 1
// End simulation
$finish;
end
// Monitor changes
initial begin
$monitor("Time = %0d, a = %b, b = %b, cin = %b, sum = %b, carry = %b", $time, a, b, cin, sum, carry);
End.
SYNTHESIS:
SIMULATION
4. Write an RTL and testbench for 2:4 decoder using data flow abstraction
RTL CODE:
module Decoder_2to4 (
input [1:0] in,
output [3:0] out
);
assign out[0] = (in == 2'b00) ? 1'b1 : 1'b0;
assign out[1] = (in == 2'b01) ? 1'b1 : 1'b0;
assign out[2] = (in == 2'b10) ? 1'b1 : 1'b0;
assign out[3] = (in == 2'b11) ? 1'b1 : 1'b0;
endmodule.
TESTBENCH:
module tb_Decoder_2to4;
reg [1:0] in;
wire [3:0] out;
Decoder_2to4 uut (
.in(in),
.out(out)
);
initial begin
// Test case 1: in = 2'b00
in = 2'b00;
#10 $display("Input: %b, Output: %b", in, out);
// Test case 2: in = 2'b01
in = 2'b01;
#10 $display("Input: %b, Output: %b", in, out);
// Test case 3: in = 2'b10
in = 2'b10;
#10 $display("Input: %b, Output: %b", in, out);
// Test case 4: in = 2'b11
in = 2'b11;
#10 $display("Input: %b, Output: %b", in, out);
// Add more test cases as needed
// Terminate simulation
#10 $finish;
end
endmodule.
SYNTHESIS:
SIMULATION:
5. Write an RTL and testbench for a 4:1 MUX using 2X1 mux
RTL CODE:-
// 2-to-1 MUX
module mux_2to1 (
input wire a, // Input A
input wire b, // Input B
input wire sel, // Select signal
output wire out // Output
);
assign out = (sel) ? b : a; // Select between a and b based on sel
endmodule
// 4-to-1 MUX using 2-to-1 MUXes
module mux_4to1 (
input wire [3:0] data, // 4-bit input data
input wire [1:0] sel, // 2-bit select signal
output wire out // Output
);
wire mux0_out, mux1_out; // Intermediate outputs of 2-to-1 MUXes
// Instantiate two 2-to-1 MUXes
mux_2to1 mux0 (
.a(data[0]),
.b(data[1]),
.sel(sel[0]),
.out(mux0_out)
);
mux_2to1 mux1 (
.a(data[2]),
.b(data[3]),
.sel(sel[0]),
.out(mux1_out)
);
// Final 2-to-1 MUX to select between the two intermediate outputs
mux_2to1 mux2 (
.a(mux0_out),
.b(mux1_out),
.sel(sel[1]),
.out(out)
);
endmodule
TESTBENCH:
module tb_mux_4to1;
// Testbench signals
reg [3:0] data;
reg [1:0] sel;
wire out;
// Instantiate the 4-to-1 MUX
mux_4to1 uut (
.data(data),
.sel(sel),
.out(out)
);
// Test sequence
initial begin
// Initialize inputs
data = 4'b0000;
sel = 2'b00;
// Apply test vectors
#10 data = 4'b1010; sel = 2'b00; // Output should be 1 (data[0])
#10 data = 4'b1010; sel = 2'b01; // Output should be 0 (data[1])
#10 data = 4'b1010; sel = 2'b10; // Output should be 1 (data[2])
#10 data = 4'b1010; sel = 2'b11; // Output should be 0 (data[3])
// End of simulation
#10;
$finish;
end
// Monitor output
initial begin
$monitor("Time: %0t | Data: %b | Sel: %b | Out: %b", $time, data, sel, out);
end
endmodule
SYNTHESIS:
SIMULATION:
6. Write an RTL for a bidirectional buffer and verify the same using testbench.
RTL CODE:
// Bidirectional Buffer
module bidirectional_buffer (
input wire clk,
input wire enable,
input wire dir, // Direction control: 0 for input, 1 for output
inout wire data // Bidirectional data line
);
// Internal signal for data
reg data_reg;
// Buffer control logic
always @(posedge clk) begin
if (enable) begin
if (dir) begin
// Output mode: Drive data onto the bus
data_reg <= data_reg;
end
else begin
// Input mode: Read data from the bus
data_reg <= data;
end
end
end
// Tri-state buffer logic
assign data = (enable && !dir) ? data_reg : 1'bz; // High impedance when not in input mode
endmodule.
TESTBENCH:
module tb_bidirectional_buffer;
// Testbench signals
reg clk;
reg enable;
reg dir;
reg [7:0] data_in;
wire [7:0] data_out;
// Instantiate the bidirectional buffer
bidirectional_buffer uut (
.clk(clk),
.enable(enable),
.dir(dir),
.data(data_out)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // 10 ns clock period
end
// Test sequence
initial begin
// Initialize signals
enable = 0;
dir = 0;
data_in = 8'h00;
// Test case 1: Write data
#10;
enable = 1;
dir = 1; // Set direction to output
data_in = 8'hA5;
// Wait for some time
#10;
enable = 0;
// Test case 2: Read data
#10;
dir = 0; // Set direction to input
enable = 1;
// Wait and observe the data
#10;
enable = 0;
// End of simulation
#10;
$finish;
end
// Monitor output
initial begin
$monitor("Time: %0t | Enable: %b | Dir: %b | Data In: %h | Data Out: %h", $time, enable, dir, data_in, data_out);
end
endmodule
SYNTHESIS:
SIMULATION:-
7. Write an RTL and testbench and testbench for a 4 bit Ripple carry adder using 1 bit full adder
RTL CODE:
`timescale 1ns / 1ps
// 1-bit Full Adder
module full_adder (
input wire a, // First input
input wire b, // Second input
input wire cin, // Carry input
output wire sum, // Sum output
output wire cout // Carry output
);
assign {cout, sum} = a + b + cin;
endmodule
// 4-bit Ripple Carry Adder
module ripple_carry_adder (
input wire [3:0] a, // 4-bit input A
input wire [3:0] b, // 4-bit input B
input wire cin, // Carry input
output wire [3:0] sum, // 4-bit sum output
output wire cout // Carry output
);
// Internal carry signals
wire c1, c2, c3;
// Instantiate 1-bit full adders
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c1)
);
full_adder fa1 (
.a(a[1]),
.b(b[1]),
.cin(c1),
.sum(sum[1]),
.cout(c2)
);
full_adder fa2 (
.a(a[2]),
.b(b[2]),
.cin(c2),
.sum(sum[2]),
.cout(c3)
);
full_adder fa3 (
.a(a[3]),
.b(b[3]),
.cin(c3),
.sum(sum[3]),
.cout(cout)
);
Endmodule.
TESTBENCH:-
module tb_ripple_carry_adder;
// Testbench signals
reg [3:0] a;
reg [3:0] b;
reg cin;
wire [3:0] sum;
wire cout;
// Instantiate the 4-bit ripple carry adder
ripple_carry_adder uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
// Test sequence
initial begin
// Initialize inputs
a = 4'b0000;
b = 4'b0000;
cin = 0;
// Apply test vectors
#10 a = 4'b0001; b = 4'b0010; cin = 0;
#10 a = 4'b0101; b = 4'b0101; cin = 0;
#10 a = 4'b1111; b = 4'b0001; cin = 1;
#10 a = 4'b1010; b = 4'b0101; cin = 1;
#10 a = 4'b1111; b = 4'b1111; cin = 0;
// End of simulation
#10;
$finish;
end
// Monitor output
initial begin
$monitor("Time: %0t | A: %b | B: %b | Cin: %b | Sum: %b | Cout: %b", $time, a, b, cin, sum, cout);
end
endmodule
SYNTHESIS:
SIMULATION:
8. Write an RTL for 4X1 mux using decoder and tri state buffer and verify the same using testbench
RTL CODE:-
// 2-to-4 Decoder
module decoder_2to4 (
input wire [1:0] sel, // 2-bit select input
output wire [3:0] dout // 4-bit output
);
assign dout = (sel == 2'b00) ? 4'b0001 :
(sel == 2'b01) ? 4'b0010 :
(sel == 2'b10) ? 4'b0100 :
4'b1000;
endmodule
// 4x1 MUX
module mux_4x1 (
input wire [3:0] data_in, // 4-bit data inputs
input wire [1:0] sel, // 2-bit select input
output wire dout // Output
);
wire [3:0] sel_out; // Outputs from the decoder
// Instantiate the 2-to-4 decoder
decoder_2to4 dec (
.sel(sel),
.dout(sel_out)
);
// Tri-state buffer for each input
assign dout = (sel_out[0]) ? data_in[0] :
(sel_out[1]) ? data_in[1] :
(sel_out[2]) ? data_in[2] :
(sel_out[3]) ? data_in[3] : 1'bz;
endmodule
TESTBENCH:
: module tb_mux_4x1;
// Testbench signals
reg [3:0] data_in;
reg [1:0] sel;
wire dout;
// Instantiate the 4x1 MUX
mux_4x1 uut (
.data_in(data_in),
.sel(sel),
.dout(dout)
);
// Test sequence
initial begin
// Initialize inputs
data_in = 4'b0000;
sel = 2'b00;
// Apply test vectors
#10 data_in = 4'b1010; sel = 2'b00; // Output should be 1
#10 data_in = 4'b1010; sel = 2'b01; // Output should be 0
#10 data_in = 4'b1010; sel = 2'b10; // Output should be 1
#10 data_in = 4'b1010; sel = 2'b11; // Output should be 0
// End of simulation
#10;
$finish;
end
// Monitor output
initial begin
$monitor("Time: %0t | Data In: %b | Sel: %b | Dout: %b", $time, data_in, sel, dout);
end
endmodule
SYNTHESIS:
SIMULATION:-
9. write 8:3 priority encoder using a structural model.
RTL CODE:-
`
module priority_encoder_8to3 (
input wire [7:0] in, // 8-bit input
output wire [2:0] out, // 3-bit encoded output
output wire valid // Indicates if any input is active
);
// Internal wires for priority levels
wire [7:0] level;
// Priority logic: Set 'level' based on highest active input
assign level[7] = in[7];
assign level[6] = in[7] | in[6];
assign level[5] = in[7] | in[6] | in[5];
assign level[4] = in[7] | in[6] | in[5] | in[4];
assign level[3] = in[7] | in[6] | in[5] | in[4] | in[3];
assign level[2] = in[7] | in[6] | in[5] | in[4] | in[3] | in[2];
assign level[1] = in[7] | in[6] | in[5] | in[4] | in[3] | in[2] | in[1];
assign level[0] = in[7] | in[6] | in[5] | in[4] | in[3] | in[2] | in[1] | in[0];
// Output assignment: Encode priority
assign out[2] = level[7] | level[6] | level[5] | level[4];
assign out[1] = level[7] | level[6] | level[5] | level[3] | level[2];
assign out[0] = level[7] | level[6] | level[4] | level[3] | level[1] | level[0];
// Valid output indicates if any input is active
assign valid = |in;
endmodule
TESTBENCH:-
module tb_priority_encoder8to3;
// Inputs
reg [7:0] in;
// Outputs
wire [2:0] out;
wire valid;
// Instantiate the priority encoder
priority_encoder8to3 uut (
.in(in),
.out(out),
.valid(valid)
);
// Initialize inputs and apply test cases
initial begin
// Apply test cases
in = 8'b00000000; #10; // Expected: out = 3'b000, valid = 0
in = 8'b00000001; #10; // Expected: out = 3'b000, valid = 1
in = 8'b00000010; #10; // Expected: out = 3'b001, valid = 1
in = 8'b00000100; #10; // Expected: out = 3'b010, valid = 1
in = 8'b00001000; #10; // Expected: out = 3'b011, valid = 1
in = 8'b00010000; #10; // Expected: out = 3'b100, valid = 1
in = 8'b00100000; #10; // Expected: out = 3'b101, valid = 1
in = 8'b01000000; #10; // Expected: out = 3'b110, valid = 1
in = 8'b10000000; #10; // Expected: out = 3'b111, valid = 1
// Test case where multiple inputs are active
in = 8'b11100000; #10; // Expected: out = 3'b111, valid = 1
// End simulation
$finish;
end
// Monitor changes
initial begin
$monitor("Time = %0d, in = %b, out = %b, valid = %b", $time, in, out, valid);
end
endmodule
Synthesis:-
Simulation:-
Lab2:Verilog
Operators:-
1. Work on Operators
RTL CODE:-
module operators (
input [3:0] a, b, // Assuming 4-bit inputs
output reg y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, y12, y13, y14, y15, y16, y17, y18, y19, y20, y21, y22, y23, y24, y25, y26, y27, y28, y29, y30
);
always @(*) begin
y0 = a && b; // Logical AND
y1 = ~b; // NOT (fixed from 'allb' to '~b')
y2 = !a; // Logical NOT
y3 = a & b; // Bitwise AND
y4 = a | b; // Bitwise OR (fixed from 'alb' to 'a | b')
y5 = ~a; // Bitwise NOT
y6 = a ^ b; // Bitwise XOR
y7 = a ~^ b; // Bitwise XNOR
y8 = &a; // Reduction AND
y9 = !a; // Logical NOT
y10 = ~&a; // Reduction NAND
y11 = ~a; // Bitwise NOT (redundant, but correct)
y12 = ^a; // Reduction XOR
y13 = ~^a; // Reduction XNOR
y14 = a << b; // Logical left shift
y15 = a >> b; // Logical right shift
y16 = a >>> b; // Arithmetic right shift
y17 = a <<< b; // Arithmetic left shift
y18 = a > b; // Greater than
y19 = a >= b; // Greater than or equal to (fixed from '4>=b' to 'a >= b')
y20 = a < b; // Less than
y21 = a <= b; // Less than or equal to
y22 = (a == b); // Equality
y23 = a - b; // Subtraction (fixed from 'al-b' to 'a - b')
y24 = (a === b); // Case equality
y25 = (a !== b); // Case inequality
y26 = a + b; // Addition
y27 = a - b; // Subtraction
y28 = a * b; // Multiplication
y29 = a / b; // Division
y30 = a % b; // Modulus
end
endmodule
synthesis:
2. Write an RTL and Testbench for ALU using arithmetic
Operators
RTL CODE:-
`timescale 1ns / 1ps
module alu(
input [7:0] a, b,
input [3:0] command_in,
input oe,
output [15:0] d_out
);
reg [15:0] out; // Declare 'out' as a register to store intermediate results
// Define command codes using parameters
parameter ADD = 4'b0000,
SUB = 4'b0001,
INC = 4'b0010,
DEC = 4'b0011,
MUL = 4'b0100,
DIV = 4'b0101,
SHL = 4'b0110,
SHR = 4'b0111,
AND = 4'b1000,
OR = 4'b1001,
INV = 4'b1010,
NAND = 4'b1011,
NOR = 4'b1100,
XOR = 4'b1101,
XNOR = 4'b1110,
BUF = 4'b1111;
// Always block to determine the output based on the command
always @(command_in or a or b) begin
case (command_in)
ADD: out = a + b;
SUB: out = a - b;
INC: out = a + 1;
DEC: out = a - 1;
MUL: out = a * b;
DIV: out = a / b;
SHL: out = a << b;
SHR: out = a >> b;
AND: out = a & b;
OR: out = a | b;
INV: out = ~a;
NAND: out = ~(a & b);
NOR: out = ~(a | b);
XOR: out = a ^ b;
XNOR: out = ~(a ^ b);
BUF: out = a;
default: out = 16'h0000;
endcase
end
// Assign the output based on the oe signal
assign d_out = (oe) ? out : 16'hzzzz;
endmodule
TESTBENCH:-
`timescale 1ns / 1ps
module alu_tb();
reg [7:0] a, b;
reg [3:0] command;
reg enable;
wire [15:0] out;
integer m, n, o;
parameter
ADD = 4'b0000,
INC = 4'b0001,
SUB = 4'b0010,
DEC = 4'b0011,
MUL = 4'b0100,
DIV = 4'b0101,
SHL = 4'b0110,
SHR = 4'b0111,
AND = 4'b1000,
OR = 4'b1001,
INV = 4'b1010,
NAND = 4'b1011,
NOR = 4'b1100,
XOR = 4'b1101,
XNOR = 4'b1110,
BUF = 4'b1111;
task initialize;
begin
a = 8'b0;
b = 8'b0;
command = ADD;
enable = 1'b0;
end
endtask
task en_oe(input en);
begin
enable = en;
end
endtask
task inputs(input [7:0] j, k);
begin
a = j;
b = k;
end
endtask
task delay;
begin
#10;
end
endtask
always @(command)
begin
#10; // Command processing delay
case (command)
ADD : $display("Command: ADD");
INC : $display("Command: INC");
SUB : $display("Command: SUB");
DEC : $display("Command: DEC");
MUL : $display("Command: MUL");
DIV : $display("Command: DIV");
SHL : $display("Command: SHL");
SHR : $display("Command: SHR");
AND : $display("Command: AND");
OR : $display("Command: OR");
INV : $display("Command: INV");
NAND : $display("Command: NAND");
NOR : $display("Command: NOR");
XOR : $display("Command: XOR");
XNOR : $display("Command: XNOR");
BUF : $display("Command: BUF");
default: $display("Invalid command");
endcase
end
initial begin
initialize;
en_oe(1'b1);
for (m = 0; m < 16; m = m + 1) begin
command = m;
delay;
end
inputs(8'd20, 8'd10);
delay;
en_oe(1'b1);
inputs(8'd25, 8'd17);
command = ADD;
delay;
$finish;
end
initial
$monitor("Input enable=%b, a=%b, b=%b, command=%b, out=%b", enable, a, b, command, out);
Endmodule
Synthesis:-
Simulation:-
Lab3:Combinational
Logic:-
1.Write behavioral description and test bench for 4:1 MUX.
RTL CODE:-
module mux4to1 (
input [1:0] sel, // 2-bit select input
input [3:0] d, // 4-bit data input
output reg y // Output
);
always @(*) begin
case (sel)
2'b00: y = d[0]; // Select input 0
2'b01: y = d[1]; // Select input 1
2'b10: y = d[2]; // Select input 2
2'b11: y = d[3]; // Select input 3
default: y = 1'b0; // Default case
endcase
end
endmodule
TESTBENCH:-
`timescale 1ns / 1ps
module tb_mux4to1;
// Inputs
reg [1:0] sel;
reg [3:0] d;
// Output
wire y;
// Instantiate the multiplexer
mux4to1 uut (
.sel(sel),
.d(d),
.y(y)
);
// Initialize inputs and apply test cases
initial begin
// Initialize inputs
sel = 2'b00;
d = 4'b0000;
// Wait for global reset to finish
#10;
// Apply test vectors
d = 4'b1010; // Data input
sel = 2'b00; #10; // Expected output: y = d[0] = 1
sel = 2'b01; #10; // Expected output: y = d[1] = 0
sel = 2'b10; #10; // Expected output: y = d[2] = 1
sel = 2'b11; #10; // Expected output: y = d[3] = 0
// Change data input and repeat tests
d = 4'b1100; // New data input
sel = 2'b00; #10; // Expected output: y = d[0] = 0
sel = 2'b01; #10; // Expected output: y = d[1] = 0
sel = 2'b10; #10; // Expected output: y = d[2] = 1
sel = 2'b11; #10; // Expected output: y = d[3] = 1
// End simulation
$finish;
end
// Monitor changes
initial begin
$monitor("Time = %0d, sel = %b, d = %b, y = %b", $time, sel, d, y);
end
endmodule
Synthesis:-
Simulation:-
2.Write a behavioral description for a 3:8 decoder and verify using a test bench.
RTL CODE:-
module decoder3to8 (
input [2:0] in, // 3-bit input
input en, // Enable signal
output reg [7:0] out // 8-bit output
);
always @(*) begin
if (en) begin
case (in)
3'b000: out = 8'b00000001;
3'b001: out = 8'b00000010;
3'b010: out = 8'b00000100;
3'b011: out = 8'b00001000;
3'b100: out = 8'b00010000;
3'b101: out = 8'b00100000;
3'b110: out = 8'b01000000;
3'b111: out = 8'b10000000;
default: out = 8'b00000000; // Default case
endcase
end else begin
out = 8'b00000000; // Outputs are all zero when enable is low
end
end
TESTBENCH:-
module tb_decoder3to8;
// Inputs
reg [2:0] in;
reg en;
// Outputs
wire [7:0] out;
// Instantiate the decoder
decoder3to8 uut (
.in(in),
.en(en),
.out(out)
);
// Initialize inputs and apply test cases
initial begin
// Initialize inputs
in = 3'b000;
en = 0;
// Wait for global reset to finish
#10;
// Enable decoder and test all input combinations
en = 1;
// Apply test vectors
in = 3'b000; #10; // Check if out = 8'b00000001
in = 3'b001; #10; // Check if out = 8'b00000010
in = 3'b010; #10; // Check if out = 8'b00000100
in = 3'b011; #10; // Check if out = 8'b00001000
in = 3'b100; #10; // Check if out = 8'b00010000
in = 3'b101; #10; // Check if out = 8'b00100000
in = 3'b110; #10; // Check if out = 8'b01000000
in = 3'b111; #10; // Check if out = 8'b10000000
// Disable decoder and check output
en = 0;
in = 3'b000; #10; // Check if out = 8'b00000000
// End simulation
$finish;
end
// Monitor changes
initial begin
$monitor("Time = %0d, in = %b, en = %b, out = %b", $time, in, en, out);
end
endmodule
endmodule
synthesis:-
simulation:-
3.Write a behavioral description and testbench 8:3 priority encoder.
RTL CODE:-
module priority_encoder8to3 (
input wire [7:0] in, // 8-bit input
output reg [2:0] out, // 3-bit output (encoded value)
output reg valid // Indicates if at least one input is active
);
always @(*) begin
// Default values
out = 3'b000;
valid = 1'b0;
// Check for the highest-priority active input
if (in[7]) begin
out = 3'b111; // Highest priority input is 7
valid = 1'b1;
end
else if (in[6]) begin
out = 3'b110; // Highest priority input is 6
valid = 1'b1;
end
else if (in[5]) begin
out = 3'b101; // Highest priority input is 5
valid = 1'b1;
end
else if (in[4]) begin
out = 3'b100; // Highest priority input is 4
valid = 1'b1;
end
else if (in[3]) begin
out = 3'b011; // Highest priority input is 3
valid = 1'b1;
end
else if (in[2]) begin
out = 3'b010; // Highest priority input is 2
valid = 1'b1;
end
else if (in[1]) begin
out = 3'b001; // Highest priority input is 1
valid = 1'b1;
end
else if (in[0]) begin
out = 3'b000; // Highest priority input is 0
valid = 1'b1;
end
else begin
valid = 1'b0; // No inputs are active
end
end
endmodule
testbench:-
module tb_priority_encoder8to3;
// Inputs
reg [7:0] in;
// Outputs
wire [2:0] out;
wire valid;
// Instantiate the priority encoder
priority_encoder8to3 uut (
.in(in),
.out(out),
.valid(valid)
);
// Initialize inputs and apply test cases
initial begin
// Apply test cases
in = 8'b00000000; #10; // Expected: out = 3'b000, valid = 0
in = 8'b00000001; #10; // Expected: out = 3'b000, valid = 1
in = 8'b00000010; #10; // Expected: out = 3'b001, valid = 1
in = 8'b00000100; #10; // Expected: out = 3'b010, valid = 1
in = 8'b00001000; #10; // Expected: out = 3'b011, valid = 1
in = 8'b00010000; #10; // Expected: out = 3'b100, valid = 1
in = 8'b00100000; #10; // Expected: out = 3'b101, valid = 1
in = 8'b01000000; #10; // Expected: out = 3'b110, valid = 1
in = 8'b10000000; #10; // Expected: out = 3'b111, valid = 1
// Test case where multiple inputs are active
in = 8'b11100000; #10; // Expected: out = 3'b111, valid = 1
// End simulation
$finish;
end
// Monitor changes
initial begin
$monitor("Time = %0d, in = %b, out = %b, valid = %b", $time, in, out, valid);
end
endmodule
synthesis:-
simulation:-
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