find the verilog code dubugging

how many errors are there in the below code

module tb()

    reg clk, reset;

    reg a,b,c;

    wire y;

    design dut (.a(a), .b(b), .c(c), .y(y), );  

    always begin

        

            clk = 1;

            #5;

            clk = 0

            #5;

        end

    endmodule

answer:-

1. missing the reset signal in always  block

2. ,missing the reset handling  in design instantiation

3. after module tb missing semicolon

4. after clk=0 the semicolon was missing

correct code:-

module tb();

    reg clk, reset;

    reg a,b,c;

    wire y;

    design dut (.a(a), .b(b), .c(c), .y(y), .reset(reset));

    always begin

        if (reset) begin

            clk = 0;

        end else begin

            clk = 1;

            #5;

            clk = 0;

            #5;

        end

    end

endmodule