Deepu creation

 find the errors in below verilog code module semi_test(a,clock, y); input a,clock; output y; always@(*) begin assign y=a; end endmodule error:= in always block and clock is not used in always block

 find the output of below verilog code if a=2'b10 and 2'b01; initial begin if(a&b) $display("hello"); else $display("world"); end output:-

 'timescale 1ns/1ps reg y; initial begin y=1'b1; forever #(15/2.0) y=~y; end output:-  7.5 because 15/2=7.5

 find the value in below verilog code always@(*) begin'x=10; y=x; x=20; #10; end     output:- x=20 and y=20

  module test(); class packet; rand bit [7:0] a; constraint c1 { foreach(a[i]) { a[i]==a[32- (4*((i+4)/4))+ (i%4)]; };} constraint c1 { foreach(a[i]) { if(i%4%)

 module test(); class packet; rand bit {31:0] a; constraint   c1 { foreach(a[i) { a[i]==a[31-i]}};} endclass packet p1=new(); initial begin p1.randomize(); $display("the value is =%p", p1.a); end endmodule