verilog important questions

 verilog  important questions:-

• 1.What is the difference between $display, $strobe and $monitor? 
• 2.Design a Verilog code for digital clock with 10 hours, 50 minutes and 20 seconds. 
• 3. How to access one txt file using 2 different functions simultaneously. 
•  4.What is the difference between Intra delay and Inter Delaay
• 5. What is the difference between blocking assignment and non-blocking assignment?
•  6.What is the difference between reg and wire datatype? 
• 7.. Why can't we call a task in function?
•  8.What is the difference between task and function?
• 9. Explain about Verilog event scheduler.
•  10.Explain about swapping two variables with and without using a temporary variable?
•  11. What is MUX? What is a full case?
•  12. What are different data types in Verilog and how they are used in different assignment Setting standards in VLSI Design one output will be high at a time.
•  13. Design any logical component having 4 input and 2 outputs using mux where only
•  14. How to exclude a part of RTL code from getting synthesized? bits and LSB 8-bits with LSB 8-bits without using 16.
•  15.There is a l6-bit reg data type variable and you need to swap LSB 8-bits with LSB8 17. Write a Verilog code for 5:1 mux.
•  16. Explain the different types of race conditions in Verilog. 
• 17. How will you write Verilog code for Mealy FSM?