find the output of the verilog code
find the output of the below code
alwaus@(clk, clr,sel)
begin
if(clr==1'b1)
else if(sel==1'b1)
q<=1'b1;
else if(clk==1'b0)
q<=1);
else
begin
end
end
output:-
d fli flop and asynchoronous reset and set
check the value 12321 is pallindrome or not by using constraint
module test(); class packet; rand bit [7:0\] a; constraint a{a inside {[0:4]};} constraint a2 { foreach(a[i]) { a[i]==a[(n-1)-i];}} endclass packet p1=new(); assert(p1.ramdomize()); $display("the value is =%p", p1.a); endmodule
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