find the syntax error and output in verilog code
function guess;
input [7:0] a,b;
if
(a>b)
#10;
guess=a;
else
#10;
guess=b;
endfunction
output or syntax error:- inside the function we cannot use delay.
check the value 12321 is pallindrome or not by using constraint
module test(); class packet; rand bit [7:0\] a; constraint a{a inside {[0:4]};} constraint a2 { foreach(a[i]) { a[i]==a[(n-1)-i];}} endclass packet p1=new(); assert(p1.ramdomize()); $display("the value is =%p", p1.a); endmodule
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