identify the verilog code output
what will be the value of y be for the entire stimuation duration
module top;
intput clk;
output reg y);
always@(posedge clk)
begin
y<=1;
y<=0;
end
endmodule
output := y=0 because it was a non blocking statement
check the value 12321 is pallindrome or not by using constraint
module test(); class packet; rand bit [7:0\] a; constraint a{a inside {[0:4]};} constraint a2 { foreach(a[i]) { a[i]==a[(n-1)-i];}} endclass packet p1=new(); assert(p1.ramdomize()); $display("the value is =%p", p1.a); endmodule
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