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find the syntax error and output in verilog code

 function guess; input [7:0] a,b; if (a>b) #10; guess=a; else #10; guess=b; endfunction output or syntax error:- inside the function we cannot use delay.

identify the verilog code output

 find the output of below code: integer a, b,c; initial begin a=10; b=20; c=15; end initial begin a<=b+c; b<=a+5; c<=a-b; end output: a=35 b=15 c=-10

identify the verilog code output

 what will be the value of y be for the entire stimuation duration module top; intput clk; output reg y); always@(posedge clk) begin y<=1; y<=0; end endmodule output :=  y=0 because it was a  non blocking statement

find the output of the verilog code

 find the output of the below code alwaus@(clk, clr,sel) begin if(clr==1'b1) else if(sel==1'b1) q<=1'b1; else if(clk==1'b0) q<=1); else begin end end output:- d fli flop and asynchoronous reset and set

find the errors in verilog code

 int a=1; b=2; c=5; d=4; e=1; i; if(a<b &&(c>d||e<b)) i=1; else if (b>c|| ( d>e && e==a0) i=2; else i=3; system.out.println(i); output:-1

find the verilog code dubugging

how many errors are there in the below code module tb()     reg clk, reset;     reg a,b,c;     wire y;     design dut (.a(a), .b(b), .c(c), .y(y), );       always begin                      clk = 1;             #5;             clk = 0             #5;         end     endmodule answer:- 1. missing the reset signal in always  block 2. ,missing the reset handling  in design instantiation 3. after module tb missing semicolon 4. after clk=0 the semicolon was missing correct code:- module tb();     reg clk, reset;     reg a,b,c;     wire y;     design dut (.a(a), .b(b), .c(c), .y(y), .reset(reset));     always begin         if (reset) begin             cl...

write a constraint such that for a memory of 1kb, 30 to 70 address would not select

 module test(); class packet; rand bit [7:0] a; constraint c1 { a inside {[0:1023]};} constraint c2 { ! {[a<30|| a>70]};} endclass packet p1=new() initial begin p1.randomize(); $display("the value is = %p", p1.a); endmodule