Deepu creation

SVA important snippet module test;                   // property p;                   //initial                  //begin                         bit a;                           bit b;                          bit c;                         bit clk,rst;                     // always@(posedge clk)                      // a_cc: assert property(@(posedge clk)  $rose(a) |=> ##1 (b[=2]) ##2 c;                      // a_cc:assert property (p);  ...

 perl important snippets:-    $a="ab"; $b="a"; if($a gt $b) { #print "true \n" } else print "false \n"; } ########snippets######### =pod      $var="Perl";      $var1='$var';      $var2= "$var";      print "$var1\n";      print "$var2\n"; =cut                  ############### arrays ################## =pod      @array=(1,2,"a","b");      print("@array\n"); =cut  ############# Hash ############### =pod                    %hash=("key"=>1,     "key2"=>2,             "key3"=>"a",     "key4"=>"b");             print(""); =cut ######## Arithmetic Opeartor ################ =pod     $x=5;     $y=10;     $z=$x+$y;     print("$z\n"); =cut ##...

  perl important snippets:-    ########snippets######### =pod      $var="Perl";      $var1='$var';      $var2= "$var";      print "$var1\n";      print "$var2\n"; =cut          

 perl important snippets:- $a="ab"; $b="a"; if($a gt $b) { #print "true \n" } else print "false \n"; }

 system verilog example thread code:- /*module threads(); initial begin fork for( int H1_pointer=0; H1_pointer<=2; H1_pointer++) begin #1  $display($time, " FIRST LOOP: vlaue of H1=%g", H1_pointer); end for(int D1_channel=2; D1_channel>=0; D1_channel--) begin #1 $display($time, " SECOND LOOP: vlaue of D1=%g", D1_channel); end join $display("@%g ouside of FORK-JOIN\n", $time); #3 $finish; end endmodule*/ /*module theads(); initial begin fork for( int H1_pointer=0; H1_pointer<=2; H1_pointer++) begin #1 $display($time, " FIRST LOOP: value of H1=%g", H1_pointer); end for( int D1_channel=2; D1_channel>=0; D1_channel--) begin #1 $display($time," SECOND LOOP: vlaue of D1=%g", D1_channel); end join_any $display("@%g outside of frok-join-any\n", $time); #3 $finish; end endmodule*/ /*module threads(); initial begin fork for( int h1_pointer=0; h1_pointer<=2; h1_pointer++) begin #1 $display($time," first loop: value of...

*module test;  int d,result;   int a=2,b=3;       function automatic mult(input int a,input int b,output int c);        c=(a*b)+2;        $display("inside function");        $display("$time =%d,a=%d,b=%d,c=%d",$time,a,b,c);    endfunction      initial      fork        begin        #1;        mult(2,3,d);        $display("//////");        $display("$time =%d,a=%d,b=%d,d=%d",$time,a,b,d);       end       begin        #2;        mult(2,4,d);        $display("//////");        $display("$time =%d,a=%d,b=%d,d=%d",$time,a,b,d);       end    join endmodule*/ /*module test;  int d,result;   int a=2,b=3;      ...

 system verilog queue using methods example code:- first we know methods: push pop push front push back pop front pop back insert delete code:- /*module test; int k, q[$] ='{1,2,3,4,5,6}; initial begin foreach(q[i]) begin k=q.pop_back(); $display("%d",k); end $display("%p",q); end endmodule :test*/

 system verilog insert one queue into another queue code:- sorting form:- /*module test; int da[]={10,2,3,4,7,6,8}; initial begin da.sort(); $display("sorting of array:"); end endmodule* system verilog insert one queue into another queue code:- /*module test; int q1[$]='{0,1,5,6,7,8}; int q2[$]='{2,3,4}; initial begin q1={q1,q2}; //q1={q1[0:1],q2[2:$]}; $display("%p",q1); end endmodule*/

constraint generate a phone number pattern:-   class PhoneNumber;   rand bit  [2:0]  area_code;    rand bit [3:0]  number;   //constraint valid_area_code {   //  area_code inside {[2:9]};} constraint valid_area_code {    area_code <=9;}  //constraint valid_number{    //    number inside{[9:0]};}  constraint valid_number{number<=9;}  function void print();                endfunction endclass PhoneNumber num=new; module test; initial  repeat(10) begin      num.randomize();    $display("phone number : %d",num.number);    $display("area code : %d", num.area_code);  num.print(); end endmodule 

  constraint natural number code:- /*----------------natural no and twice odd no--------- class b1; rand int a[]; constraint a1{a.size==(10);} constraint a2{foreach (a[i])                         if(i%2==0)                             a[i]==i; // a[i]==i; // a[i]==i+1; else if(i%2==1) a[i]==i+1;} endclass b1 a3; module test; initial begin a3=new; assert(a3.randomize()); $display("the value %p",a3.a); end endmodule */ constraint twice odd number code:- /*class b1; rand bit[7:0] a[]; constraint a1{a.size==(10);} constraint a2{foreach (a[i])                         if(i%2==0)                                 a[i]==i;} endclass b1 a3; module test; initial begin a3=new; assert(a3.randomize()); $display("the value ...

 constraint odd number code:- */ /*---------------odd--------------*/ /* class b1; rand int a[]; constraint a1{a.size==(10);} constraint a2{foreach (a[i])                         if(i%2==1)                                 a[i]==i;} endclass b1 a3; module test; initial begin a3=new; assert(a3.randomize()); $display("the value %p",a3.a); end endmodule */

  constraint even number code:- ///* ---even----- clas s Packet;   rand bit[7:0] payload[]; //dynamic array   constraint packet_cnstr {      payload.size inside {[2:5]};      payload.sum == 100;      foreach (payload[kk])         payload[kk] inside {[1:100]}; // non-negative integers   } endclass module test; initial begin    repeat (5) begin // generate 5 packets         Packet p1;         p1 = new(); end if (p1.randomize()) begin            $write("payload has %0d elements: ", p1.payload.size);            for (int ii=0; ii < p1.payload.size; ii++)               $write("%2d ", p1.payload[ii]);            $display;         end else begin            $display("randomization faile...

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  /*import uvm_pkg::*; `include "uvm_macros.svh" class my_xtn extends uvm_sequence_item; rand bit [3:0]addr; rand bit [7:0] data; constraint  valid_addr{addr inside {[2:13]};} constraint  valid_data {data inside {[15:150]};} 0  `uvm_object_utils_begin(my_xtn) `uvm_field_int(addr,UVM_ALL_ON) `uvm_field_int(data,UVM_ALL_ON) `uvm_object_utils_end function new(string name="my_xtn"); super.new(name); endfunction endclass class my_generator extends uvm_component; uvm_blocking_put_port #(my_xtn) put_port; `uvm_component_utils(my_generator) function new(string name="my_generator", uvm_component parent); super.new(name, parent); put_port=new("put_port",this); endfunction virtual task run_phase(uvm_phase phase); my_xtn xtn; for( int i=0; i<10; i++) begin xtn=my_xtn::type_id::create("xtn"); phase.raise_objection(this); #10; put_port.put(xtn); phase.drop_objection(this); end endtask endclass class my_driver extends uvm_component; uvm_blocking_pu...

uvm example snippets by using macros and without macros:- /*import uvm_pkg::*; `include "uvm_macros.svh" class my_xtn extends uvm_sequence_item; rand bit [3:0]addr; rand bit [7:0] data; string str; constraint  valid_addr{addr inside {[2:13]};} constraint  valid_data {data inside {[15:150]};} `uvm_object_utils_begin(my_xtn) `uvm_field_int(addr,UVM_ALL_ON) `uvm_field_int(data,UVM_ALL_ON) `uvm_object_utils_end function new(string name="my_xtn"); super.new(name); endfunction endclass module xtn_test(); my_xtn xtn,xtn1,xtn2,xtn3; bit a[]; int unsigned b[]; initial begin function new("string name= xtn=my_xtn::type_id::create(); assert(xtn.randomize()); xtn.print(); $display("%s", xtn.sprint()); xtn.str=$sformatf("%s",xtn.sprint()); $display("str=%s", xtn.str); $cast(xtn1,xtn.clone()); xtn1.print(); $display(xtn.compare(xtn1)); xtn2=my_xtn::type_id::create("xtn2"); xtn2.copy(xtn1); xtn2.print(); xtn2.pack(a); $display(a); xtn2.p...

 verilog  important questions:- 1.What is the difference between $display, $strobe and $monitor?  2.Design a Verilog code for digital clock with 10 hours, 50 minutes and 20 seconds.  3. How to access one txt file using 2 different functions simultaneously.   4.What is the difference between Intra delay and Inter Delaay 5. What is the difference between blocking assignment and non-blocking assignment?  6.What is the difference between reg and wire datatype?  7.. Why can't we call a task in function?  8.What is the difference between task and function? 9. Explain about Verilog event scheduler.  10.Explain about swapping two variables with and without using a temporary variable?  11. What is MUX? What is a full case?  12. What are different data types in Verilog and how they are used in different assignment Setting standards in VLSI Design one output will be high at a time.  13. Design any logical component having 4 input and...

digital electronics important questions:- 1.  Design a posedge detector circuit.? 2. Consider in a 4:1 mux, if the select lines are A and B and inputs are c, C, c', c' whlch gate is inferred?3. How to represent a (8) into a sign-magnitude form?  4. Find the grey-code for 20H? 5. What is the De-morgans 1st law equivalent to? required?  6.When will AND gate work as OR gate? Explain about the input combinations?  7.. How many 2:1 mux is recuired fo I for 8:1 mux? 8. (396)10 = ()13 ? 9. Write the 2's complement form of 1000?. 10. Which gates are used to represent a half adder?  11. Write the hexadecimal m (4096*12) ? 12. What is a FIF0? ma representation of X. where X* 10+ (16°7) + (256°9)?   13. What is the difference between grey code, one hot encoding and binary code?  14. What is the difference between Decoder and Demultiplexer?  15, What is a ripple counter? 16. What is the difference between Moore and Mealy type FSM?  17. Explain the c...

 verilog interview questions:- 1. differnce between reg and wire? 2. difference between blocking and non blocking assignments? 3. what is `timescale? 4. what are the data types in verilog? 5.  write the code for d flipflop? 6. how many methods are there to write the verilog code? 7. write the verilog code for fsm 110? 8.write the verilog code for synchronours FIFO? 9. write the verilog code for SIPO? 10. write the verilog code for synchronous D flipflop? 11.  Write a Verilog code forD flip flop?.   12. Write a Verilog code for swapping numbers using Non- blocking assignments. ?  13. Write a Verilog code for counter which counts 0-6? . 14. What is the difference between asynchronous reset and synchronous reset?  15. Write a Verilog code for asynchronous D- FF and synchronous D- FF.?  16. What is the difference between blocking and Non-blocking assignments?  17.Write a Verilog code for a 4bit ripple counter.? 18. Write a Verilog code for a D- l...

 verilog important codes:- Lab1:Verilog Abstraction Levels:- 1. Write a verilog code  for a half adder adder using data flow abstraction using testbench 2. Write a verilog for a 1 bit full adder using 2 half adder and 1 or gate and verify   using testbench 3. Write a verilog code  for a full  adder adder using data flow abstraction and verify   using testbench 4. Write an RTL and testbench for 2:4 decoder  using data flow abstraction 5. Write an RTL  and testbench  for a 4:1 MUX using 2:1 MUX 6. Write an RTL for a bidirectional buffer and verify the same using testbench. 7. Write an RTL and testbench  and testbench for a 4 bit Ripple carry adder using 1 bit   full adder 8. Write an RTL for 4X1 mux using decoder and  tri state buffer and verify the same      using testbench 9. write 8:3 priority  encoder using a structural model Lab2:Verilog Operators:-  1. Wo...