Deepu creation

find the syntax error in the below verilog code always@(clk) begin a=x; a<=1; end initial $display(a); initial $monitor(a); output:-

 find the errors in below verilog code module semi_test(a,clock, y); input a,clock; output y; always@(*) begin assign y=a; end endmodule error:= in always block and clock is not used in always block

 find the output of below verilog code if a=2'b10 and 2'b01; initial begin if(a&b) $display("hello"); else $display("world"); end output:-

 'timescale 1ns/1ps reg y; initial begin y=1'b1; forever #(15/2.0) y=~y; end output:-  7.5 because 15/2=7.5

 find the value in below verilog code always@(*) begin'x=10; y=x; x=20; #10; end     output:- x=20 and y=20

  module test(); class packet; rand bit [7:0] a; constraint c1 { foreach(a[i]) { a[i]==a[32- (4*((i+4)/4))+ (i%4)]; };} constraint c1 { foreach(a[i]) { if(i%4%)

 module test(); class packet; rand bit {31:0] a; constraint   c1 { foreach(a[i) { a[i]==a[31-i]}};} endclass packet p1=new(); initial begin p1.randomize(); $display("the value is =%p", p1.a); end endmodule

 function guess; input [7:0] a,b; if (a>b) #10; guess=a; else #10; guess=b; endfunction output or syntax error:- inside the function we cannot use delay.

 find the output of below code: integer a, b,c; initial begin a=10; b=20; c=15; end initial begin a<=b+c; b<=a+5; c<=a-b; end output: a=35 b=15 c=-10

 what will be the value of y be for the entire stimuation duration module top; intput clk; output reg y); always@(posedge clk) begin y<=1; y<=0; end endmodule output :=  y=0 because it was a  non blocking statement

 find the output of the below code alwaus@(clk, clr,sel) begin if(clr==1'b1) else if(sel==1'b1) q<=1'b1; else if(clk==1'b0) q<=1); else begin end end output:- d fli flop and asynchoronous reset and set

 int a=1; b=2; c=5; d=4; e=1; i; if(a<b &&(c>d||e<b)) i=1; else if (b>c|| ( d>e && e==a0) i=2; else i=3; system.out.println(i); output:-1

how many errors are there in the below code module tb()     reg clk, reset;     reg a,b,c;     wire y;     design dut (.a(a), .b(b), .c(c), .y(y), );       always begin                      clk = 1;             #5;             clk = 0             #5;         end     endmodule answer:- 1. missing the reset signal in always  block 2. ,missing the reset handling  in design instantiation 3. after module tb missing semicolon 4. after clk=0 the semicolon was missing correct code:- module tb();     reg clk, reset;     reg a,b,c;     wire y;     design dut (.a(a), .b(b), .c(c), .y(y), .reset(reset));     always begin         if (reset) begin             cl...

 module test(); class packet; rand bit [7:0] a; constraint c1 { a inside {[0:1023]};} constraint c2 { ! {[a<30|| a>70]};} endclass packet p1=new() initial begin p1.randomize(); $display("the value is = %p", p1.a); endmodule

 module test(); class packet; rand int a; int b[$]; constraint c1 { ainside {[0:100]};} constraint c2 {! )a inside {b});} function void post_randomize(); b.push_front(a); $display("printnvaluen%od", a); if(b.size>=101) b.delete(101); endfunction endclass packet p1=new() initial begin for(int i=0; i<100; i++) begin p1.randomize(); end end endmodule p1.randomize();

 module test(); class packet; bit rand [7:0] a; constraint c1 { a inside {[0:500]};} constraint c2 { foreach (a[i]) if(i>1) a[i]==prime(i);} endclass packet p1=new(); assert(p1.randomize()); $display("the value is =%p", p1.a); endmodule